Schedule for ESE 355 - Spring 2005


 
                         Week
                                   Monday
                                      Wednesday
Friday
1)               01/24-01/30 Introduction to design of VLSI systems and circuits.
(Homework 1 starts)
 The VLSI design flow.
 MOSFET Transistor. Static behavior.
2)               01/31-02/06 MOSFET Transistor. Static behavior.
Lab class (Logic & transistor level simulation. IRSIM. SPICE)
 MOSFET Transistor. Dynamic behavior.
 
 		 Recitation: The MOSFET Transistor

           
 
3)               02/07-02/13 CMOS Inverter. Static behavior.
Lab class (Circuit sizing for timing performance) 
 CMOS Inverter. Static behavior.  CMOS Inverter. Dynamic behavior.
4)               02/14-02/20 CMOS Inverter. Propagation delay.
Lab class (Introduction to layout design. Design rules. MAGIC) 
 
 CMOS Inverter. Power consumption.
(Homework1 is due)
(Homework 2 starts)
 Recitation: CMOS inverter
 
5)               02/21-02/27 Combinational Logic Gates. Complementary CMOS design 
 Lab class (Layout design of basic digital gates) 
 Combinational Logic Gates. Complementary CMOS design 
 Layout techniques for complex gates. 
6)               02/28-03/06 Combinational Logic Gates. Dynamic CMOS. Principles.
(Homework 2 is due)
(Homework 3 starts)
Lab class (Advanced features in MAGIC) 
Combinational Logic Gates. Dynamic CMOS. Performance. 
 Combinational Logic Gates. Dynamic CMOS. Cascading.
7)               03/07-03/13 Combinational Logic Gates. Bit-slice design. Pipelining. Scaling.
Lab class (Design of pipelined circuits)
 Combinational Logic. Power consumption.  Recitation: Combinational logic gates            
8)               03/14-03/20 Design of Sequential Circuits. flip-flops. master-slave ff.       
Lab class (Design of miniprocessor) 
Design of Sequential Circuits. CMOS static flip-flops.
 Design of Sequential Circuits. CMOS static flip-flops.
(Homework 3 is due)
(Homework4 is handed over)
(Miniproject starts)
9)               03/21-03/27
Spring break
Spring break
 Spring break
10)             03/28-04/03 Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop.
Lab class (processor I/O; pad frame)
 Design of Sequential Circuits. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy.
  Recitation: Sequential Circuits
11)             04/04-04/10 Design for Testability.
 Design for Testability
 Recitation: Sequential Circuits
12)             04/11-04/17
Lab class.
Mini Project Review 1 
(includes pinout & floorplan.logic diagram & block diagrams. timing diagram. bit slicing scheme. chip testing strategy) 
 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology.
 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology.
13)             04/18-04/24 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology.
Lab class (miniprocessor design)
 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
14)             04/25-05/01
No classes in session
 Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
Lab class (miniprocessor design)
 Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
15)             05/02-05/08 Recitation: Overall Review
Lab class (miniprocessor design)
 Recitation: Overall Review
Lab class
 Mini Project is due & project defense