Schedule for ESE 330
Fall 2004
 
                         Week
Monday
 Wednesday
Friday
1)             08/30-09/05
Introductory class
 Introduction to design of VLSI systems and circuits. Design Methodology. CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Introduction to design of VLSI systems and circuits. Quality Metrics of a Digital Design.
2)             09/06-09/12
Labor Day
 The Manufacturing Process. Manufacturing CMOS Integrated Circuits. Design Rules. The Manufacturing Process. Manufacturing CMOS Integrated Circuits. Design Rules.
3)             09/13-09/19 The Manufacturing Process. Manufacturing CMOS Integrated Circuits. Design Rules.  The Manufacturing Process. Packaging Integrated Circuits. Trends in Process Technology.
(Hw 1 is handed over)
No class
4)             09/20-09/26
The MOSFET Transistor. Static behavior. 
 The MOSFET Transistor. Dynamic behavior. The MOSFET Transistor. Dynamic behavior.Secondary effects.
5)             09/27-10/03 The MOSFET Transistor. Dynamic behavior.SPICE models for the MOS transistor. Small-signal models.  The CMOS Inverter. Static behavior.
The CMOS Inverter. Static behavior. Operation regions.
(Hw 1 is due)
(Hw 2 is handed over)
6)             10/04-10/10  The CMOS Inverter. Static behavior. Switching threshold voltage.
The CMOS Inverter. Static behavior. Noise margins
 The CMOS Inverter. Dynamic behavior. Propagation delay. 
7)             10/11-10/17 The CMOS Inverter. Dynamic behavior. Propagation delay.  The CMOS Inverter.Power consumption. Combinational Logic Gates. Complementary CMOS.
(Hw 2 is due)
(Hw 3 is handed over)
8)             10/18-10/24 Recitation (Hw 2) Preparation for midterm exam (Ch 1; 2&5)
Midterm exam
9)             10/25-10/31  Combinational Logic Gates. Complementary CMOS design  Combinational Logic Gates. Complementary CMOS design. Layout design.   Combinational Logic. Ratioed Logic.
10)           11/01-11/07 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading.
(Hw 3 is due)
(Hw 4 is handed over)
 Recitation (hw3)
Combinational Logic Gates. Pass transistor logic. 
11)           11/08-11/14 Combinational Logic Gates. Pipelining. Bitslice design. Combinational Logic Gates. Power Dissipation. Design of Sequential Circuits.  flip-flops. master-slave ff. CMOS static flip-flops.
12)           11/15-11/21 Design of Sequential Circuits.Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. Design of Sequential Circuits. Dynamic two-phase flip flop. C2MOS latch.   
Design of Sequential Circuits. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy. 
(Hw 4 is due)
(Hw 5 is handed over)
13)           11/22-11/28 Recitation (hw4) Arithmetic Building Blocks. data paths in digital processor architectures. binary adders.
No class
14)           11/29-12/05 Arithmetic Building Blocks. data paths in digital processor architectures. multiplier. Arithmetic Building Blocks. data paths in digital processor architectures. multiplier. Arithmetic Building Blocks. data paths in digital processor architectures. shifter.
15)           12/06-12/12 Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter.  Arithmetic Building Blocks. Power considerations & design trade-offs Recitation (hw 5); 
Preparation for final exam
(Hw 5 is due)