Schedule for ESE 355
 
 
                         Week
                                   Monday
                                      Wednesday
Friday
1)                 01/23-01/27 Introduction to design of VLSI systems and circuits. The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Small-signal models.
2)                 01/28-02/03 The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Small-signal models.
Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE)		 The CMOS Inverter. Static behavior. Dynamic behavior. 

Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE)

 The CMOS Inverter. Static behavior. Dynamic behavior. 

           (Homework 1 is handed over)
3)                 02/04-02/10 The CMOS Inverter. Static behavior. Dynamic behavior.  The CMOS Inverter. Dynamic behavior. Propagation delay. Power consumption. Combinational Logic Gates. Complementary CMOS design 
4)                 02/11-02/17 Combinational Logic Gates. Complementary CMOS design 
        (Homework1 is due)		 Layout techniques for complex gates. 
Out of town
5)                 02/18-02/24 Combinational Logic Gates. Complementary CMOS design
Lab class (Introduction to layout design. Design rules. MAGIC)		 Combinational Logic Gates. Complementary CMOS design
 Lab class (Introduction to layout design. Design rules. MAGIC)		 Combinational Logic Gates. Ratioed logic. Pass-transistor Logic. 
6)                 02/25-03/03 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading. 
            (Homework 2 is handed over)
 
 
            Out of town
 
 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading.
7)                 03/04-03/10 Combinational Logic Gates. Bit-slice design. Pipelining. Scaling. Power consumption.         
                     		 Combinational Logic Gates. Bit-slice design. Pipelining. Scaling. Power consumption.                      Midterm 1
              
8)                 03/11-03/17 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops.        Lab class (Introduction to CADENCE)
(Homework 2 is due)
(Homework 3 is handed over)                         		 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops.                  
Lab class (Introduction to CADENCE)                           		 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops. 
9)                 03/18-03/24 Design of Sequential Circuits. Implementation with PLA structures. Application. 
        (Homework 3 is due)
       (Mini project is handed over)
       (Homework4 is handed over)               		 Design of Sequential Circuits. Implementation with PLA structures. Application.  Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy.  
                 
10)               04/01-04/07  Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy.  
 		 Design for Testability.
                            		 Design for Testability.
        (Homework4 is handed over) 
11)               04/08-04/14 Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs.
 		 Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs. Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs.
12)               04/15-04/21                                    Lab class.
                         Mini Project Review 1 
(includes pinout & floorplan.logic diagram & block diagrams. timing diagram. bit slicing scheme. chip testing strategy) 		 Interconnect. Interconnect parasitic.  Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology.
13)               04/22-04/28 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
14)               04/29-05/05 Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.  CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools. CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools.
15)               05/06-05/08 CAD for VLSI Design. High-level synthesis. Commercial tools.                                        Lab class
                               Mini Project is due