Schedule for ESE 355
Spring 2004
 
 
                         Week
                                   Monday
                                      Wednesday
Friday
1)               01/26-02/01 Introduction to design of VLSI systems and circuits. The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Small-signal models.  The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Small-signal models. 
2)               02/02-02/08 The CMOS Inverter. Static behavior. Dynamic behavior. 
Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE)
(Homework 1 is handed over)
 The CMOS Inverter. Static behavior. Dynamic behavior. 
Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE)
 
Out of town 

           
 
3)               02/09-02/15 The CMOS Inverter. Static behavior. Dynamic behavior.  The CMOS Inverter. Dynamic behavior. Propagation delay. Power consumption. Combinational Logic Gates. Complementary CMOS design 
4)               02/16-02/22 Combinational Logic Gates. Complementary CMOS design. 
Lab class (Introduction to layout design. Design rules. MAGIC)
(Homework1 is due)
(Homework 2 is handed over) 
 Bit-slice design. Layout techniques for complex gates. 
Lab class (Introduction to layout design. Design rules. MAGIC)		 Combinational Logic Gates. Complementary CMOS design 
 
5)               02/23-02/29 Combinational Logic Gates. Complementary CMOS design 
 		 Combinational Logic Gates. Ratioed logic. Pass-transistor Logic. 
Out of town
6)               03/1-03/07 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading.
(Homework 2 is due)
(Homework 3 is handed over)
           
Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading.
 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading.
7)               03/08-03/14
 Combinational Logic Gates. Pipelining. Scaling. Power consumption. 		 Combinational Logic. Power consumption.                    Midterm 1
8)               03/15-03/21 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops.       
Lab class (Introduction to CADENCE)
(Homework 3 is due)
(Homework4 is handed over)
 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops. 
Lab class (Introduction to CADENCE)		 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops. 
9)               03/22-03/28 Design of Sequential Circuits. Implementation with PLA structures.Application. 
       (Miniproject is handed over)		 Design of Sequential Circuits. Implementation with PLA structures.Application.  Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy. 
10)             03/29-04/04  Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy.  Design for Testability. Design for Testability.
(Homework4 is due)
11)             04/05-04/11

Spring break

Spring break

Spring break
12)             04/12-04/18 Lab class.
Mini Project Review 1 
(includes pinout & floorplan.logic diagram & block diagrams. timing diagram. bit slicing scheme. chip testing strategy) 		 Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs.  Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs.
13)             04/19-04/25 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology. Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
14)             04/26-05/02 Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems. CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools.
15)             05/03-05/09 CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools. CAD for VLSI Design. High-level synthesis. Commercial tools. Lab class
      Mini Project is due & project defense