Week  Tuesday  Thursday 
1) 01/2401/28  Introduction to design of VLSI systems and circuits.  
2) 01/2902/04  The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Smallsignal models.  Canceled (out of town) 
3) 02/0502/11  The CMOS Inverter. Static behavior. Dynamic behavior.  The CMOS Inverter. Dynamic behavior. Propagation delay. Power consumption. 
4) 02/1202/18  Combinational Logic Gates. Complementary CMOS design
(Homework 1 is handed over) 
Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE) 
5) 02/1902/25  Combinational Logic Gates. Complementary CMOS design  Combinational Logic Gates. Ratioed logic. Passtransistor Logic.

6) 02/2603/04  Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading. ( Homework 1 is due )  Combinational Logic Gates. Bitslice design. Pipelining. Scaling. Power consumption. 
7) 03/0503/11  Layout techniques for complex gates.
(Homework 2 is handed over) 
Lab class (Introduction to layout design. Design rules. MAGIC) 
8) 03/1203/18  Midterm 1 
Canceled (out of town)
(Homework 2 is due) 
9) 03/2604/01  Design of Sequential Circuits. flipflops. masterslave ff.
CMOS static flipflops.
(Mini project is handed over) (Homework 3 is handed over) 
Lab class (Introduction to controller generation. MAPLEX) 
10) 04/0204/08  Design of Sequential Circuits. Implementation with PLA structures.
Application.

Design for Testability.
(Homework 3 is due) 
11) 04/0904/15  Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic twophase flip flop. C2MOS latch. NORACMOS structure. True singlephase clocked logic. Clocking strategy.  Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design tradeoffs. 
12) 04/1604/22 
Lab class.
Mini Project Review 1 (includes pinout & floorplan.logic diagram & block diagrams. timing diagram. bit slicing scheme. chip testing strategy) 
Interconnect. Interconnect parasitic. 
13) 04/2304/29  Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology.  Timing Issues in Digital Circuits. Clock Skew. Single & twophase clocking. countering of clock skew problems. 
14) 04/3005/06  Timing Issues in Digital Circuits. Clock Skew. Single & twophase clocking. countering of clock skew problems.  CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools. 
15) 05/0705/13  CAD for VLSI Design. Highlevel synthesis. Commercial tools. 
Lab class
Mini Project is due 