Schedule for ESE 555
 
 
                         Week                                    Tuesday                                       Thursday
1)                 01/24-01/28 Introduction to design of VLSI systems and circuits.
2)                 01/29-02/04 The MOSFET Transistor. Static behavior. Dynamic behavior.Secondary effects. SPICE models for the MOS transistor. Small-signal models.                             Canceled (out of town)
3)                 02/05-02/11 The CMOS Inverter. Static behavior. Dynamic behavior.  The CMOS Inverter. Dynamic behavior. Propagation delay. Power consumption.
4)                 02/12-02/18 Combinational Logic Gates. Complementary CMOS design
                      (Homework 1 is handed over)		 Lab class (Introduction to logic & transistor level simulation. IRSIM. SPICE) 
5)                 02/19-02/25 Combinational Logic Gates. Complementary CMOS design Combinational Logic Gates. Ratioed logic. Pass-transistor Logic.  
                                
6)                 02/26-03/04 Combinational Logic Gates. Dynamic CMOS. Principles. Performance. Cascading. ( Homework 1 is due ) Combinational Logic Gates. Bit-slice design. Pipelining. Scaling. Power consumption.
7)                 03/05-03/11 Layout techniques for complex gates.
                       (Homework 2 is handed over)		 Lab class (Introduction to layout design. Design rules. MAGIC)
8)                 03/12-03/18                                      Midterm 1                              Canceled (out of town)
                               (Homework 2 is due)
9)                 03/26-04/01 Design of Sequential Circuits. flip-flops. master-slave ff. CMOS static flip-flops. 
                        (Mini project is handed over) 
                        (Homework 3 is handed over)		 Lab class (Introduction to controller generation. MAPLEX)
10)               04/02-04/08 Design of Sequential Circuits. Implementation with PLA structures. Application.
                        
 		 Design for Testability. 
                             (Homework 3 is due)
11)               04/09-04/15 Design of Sequential Circuits. Dynamic sequential circuits. Pseudo static latch. Dynamic two-phase flip flop. C2MOS latch. NORA-CMOS structure. True single-phase clocked logic. Clocking strategy.  Arithmetic Building Blocks. data paths in digital processor architectures. binary adders. multiplier. shifter. Power considerations & design trade-offs.
12)               04/16-04/22                                    Lab class.
                         Mini Project Review 1 
(includes pinout & floorplan.logic diagram & block diagrams. timing diagram. bit slicing scheme. chip testing strategy) 		 Interconnect. Interconnect parasitic. 
13)               04/23-04/29 Interconnect. Crosstalk. Resistive parasitic. Inductive parasitic. Packaging technology. Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.
14)               04/30-05/06 Timing Issues in Digital Circuits. Clock Skew. Single & two-phase clocking. countering of clock skew problems.  CAD for VLSI Design. Circuit Synthesis. Logic Synthesis. Commercial tools.
15)               05/07-05/13 CAD for VLSI Design. High-level synthesis. Commercial tools.                                        Lab class
                               Mini Project is due