Project Description
 
 

                                                                          Placement                                                                                  Global Routing
 

Objective	Simulated annealing	Partitioning based	Integer Linear Programming	Objective	Lee's algo	Soukup's algo	Hanlock's algo
Minimize total wirelength	Group 4	Group 2	Group 8	Minimize total wirelength	Group 3	Group 9	Group 10
Minimze length of  longest interconnection wire	Group 1	Group 5	Group 6	Minimize length of  longest interconnection wire	Group 11	Group 12	Group 7
Routability		Everybody
Total IC area is fixed	Group 1	Group 5	Group 6
Minimize total IC area	Group 4	Group 2	Group 8

Inputs

• circuit netlist, area, timing info about each building block, position of I/O pins on the pad frame
• full custom design style is assumed

Additional Requirements

• groups have to decide the interfacing of their software module (files that are input/output, data formats etc)
• what kind of info should be produced by unroutable layouts to guide the placement process?

Benchmark Examples

"Dragon" Benchmark

MARCO GSRC Benchmark Examples

Layout Synth'92

Layout Synth'90

Teaming of Groups

• Group 3 + Group 4
• Group 8 + Group 10
• Group 6 + Group 7
• Group 2 + Group 9
• Group 1 + Group 11
• Group 5 + Group 12