Project Description

                                                                         Placement                                                                                 Global Routing
 

Objective	Simulated annealing	Partitioning based	Objective	Soukup's algo	Hanlock's algo
Minimize total wirelength	Group 4	Group 2	Minimize total wirelength	Group 9	Group 3
Minimze length of  longest interconnection wire	Group 1	Group 5	Minimize length of  longest interconnection wire	Group 8	Group 7
Routability		Everybody
Total IC area is fixed	Group 1	Group 5
Minimize totalIC area	Group 4	Group 2

Groups:

Group 1: Lili Zhou, Shanshan Xu.
Group 2: Aashish Shah, Prakash Shekar, Balasubramanian Natarajan.
Group 3: Baskar Mukherjee, Kartik Rao, Puloma Mukherjee.
Group 4: Prashant Kher, Mandeep Singh Sawhney, Samir Raut.
Group 5: Pallavi Gokhale, Gopa Dutta, Saujanya Gosangari.
Group 6: -
Group 7: Krishna Kumar Nair, Praveen Ranachandran, Sheela Rangarajan.
Group 8: Prakshep Padia, Prachi Ughade, Vaishali Wani.
Group 9: Nima Shah, Tejas Brahmbhatt, Venkat.

Inputs

• circuit netlist, area, timing info about each building block, position of I/O pins on the pad frame
• full custom design style is assumed

Additional Requirements

• groups have to decide the interfacing of their software module (files that are input/output, data formats etc)
• what kind of info should be produced by unroutable layouts to guide the placement process?

Benchmark Examples

"Dragon" Benchmark

MARCO GSRC Benchmark Examples

Layout Synth'92

Layout Synth'90

What to hand in?

A technical report must be handed in. The report will contain following sections:

• Introduction and Problem Statement.
• Related Work.
• Propsoed solution to the problem and relevant implementation issues.
• Experimental results.
• Conclusion.
• Bibliography.