Start date: 09/24/2003
Due date: 10/15/2003

1. Introduction

The goal of the your first project is to get familiarized with SystemC language, and SystemC behavioral
modeling. You will develop, code, and simulate a (simpler) processor architecture. Simulation results
should address (1) verifying the correctness of your model, and (2) collecting data about the timing
performance of your processor (such as, timing of each instruction).

Each of you will work in a team of 2 students. You will have to find a partner, and send me an email
at adoboli@ece.sunysb.edu before 09/29/2003. You will email me your project preference, but i will
make the final decision to have equally "balanced" assignments.

You will submit a project report presenting your (a) design solution, (b) SystemC model, (c) model
verification strategy, and (d) simulation results.

Finally, before starting the actual SystemC coding, I suggest that each team meets me during office
hours (Mon, Wed 1-3pm) to present the block structure of their specification.

2. Project Topics

Processor 1:

This project addresses a simplified Intel 80x86 processor architecture. You will use the description
offered in J. Hennessy, D. Patterson, "Computer Architecture - A Quantitative Approach";
Second Edition, 1996, Appendix D. The model will be at the instruction set level.

The architecture will include the following:
    a) the register set presented on page D-3
    b) all addressing modes as shown on page D-4
    c) 80x86 integer operations, as explained in pages D-7 to D-9
    d) instruction words will follow the encoding in Figure D.7

Processor 2:

This project addresses a simplified version of PowerPC processor. The reference material is
in W. Stallings, "Computer Organization and Architecture", 5th Edition, 2000. The model will
be at the instruction level.

The simplified architecture includes the following:
    a) the instruction set as shown in Table 9.11, page 357. Do not consider floating point instructions.
    b) addressing modes are shown in Figure 10.9, page 401.
    c) the register set is shown in Figure 11.22, page 444
    d) data cache, only (as described in Figure 4.25, page 136) 

Processor 3:

This project focuses on the PICmicro microcontroller instruction set. You will use M. Predko,
"Programming and Customizing PICmicro Microcontrollers", McGraw-Hill, 2002 as a reference.
For this project, it is acceptable to develop RTL models, if one wants to. The instruction set is
presented in Chapter 4, starting at page 103.

Your model will include the following:
    a) data-movement instructions
    b) data-processing instructions
    c) execution change operators
    d) processor-control instructions
 
Processor 4:

This project uses a simplified version of the vector processor presented in J. Hennessy, D. Patterson,
"Computer Architecture - A Quantitative Approach"; Second Edition, 1996, Appendix B. You will
refer to the DLXV vector instructions shown in Figure B.3, page B-7. Also, refer to Sections B.3 and
B.5 for more details. The basic architecture is shown in Figure B.1, page B-4.

3. Simulation

In your report, each team should provide sufficient evidence that the SystemC model is correct. You will
have to carefully select a set of test benchmarks (such as, small programs), which exercise all features of
your SystemC model (like instructions, addressing modes etc).

Similarly, you will use a set of benchmarks to measure the timing performance. You can use J. Hennessy,
D. Patterson,  "Computer Architecture - A Quantitative Approach"; Second Edition, 1996, as a reference.

4. Report

You will submit in class a hard copy of the report, and also email me a soft copy at adoboli@ece.sunysb.edu.
The report will present the architecture you are modeling, the structure of your SystemC model, the testbench
for correctness verification, and the testbench for timing characterization. Please include figures, waveforms
as needed. The report should not exceed 12 pages, 11pt.