1) The IBM Core Connect Standard.
2) P. Guerrier, A. Greiner, " A Generic Architecture for On-Chip Packet-Switched Interconnections".
3) P. Restle et. al,"A clock distribution network for microprocessors", Journal of Solid State Circuits (JSSC), Vol. 36      pgs 792-799, May    2001.
4) C Sevensson,"Optimal voltage-swing on on-chip and off-chip interconnect",IEEE JSSC,Vol. 36, pgs 1108-1112, July 2001.
5) N. Kurd et. al,"A Multigigahertz clocking scheme for the Pentium 4 microprocessor", JSSC, Vol. 36, Nov. 2001, pgs 1647-1653.
6) M. Chatterjee et. al,"Buffer assignment algorithms for data driven ASIC's", IEEE Transactions on Computers, Jan 2000.
7) P. Guerrier, A. Greiner,"A Generic Architecture for on-chip Packet-Switched Interconnections".
8) J. Leijten et. al,"Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor",Proceedings of DATE, 1998.
9) T. Burd et. al,"Dynamic Voltage Scaled Microprocessor Systems", IEEE JSSC, Nov 2000, pgs 1571-1580 , Vol 35.
10) R. Heald et. al,"A Third Generation SPARC V9 64-bit microprocessor", Nov. 2000, IEEE JSSC, pgs 1526-1538, Vol. 35.
11) G. Cao,"Proactive power-aware cache management for mobile computing systems", IEEE Transactions on Computers, June 2002.
12) L. Codrescu,"Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications",IEEE Transactions on Computers, Jan. 2001.
13) C.  Benveniste et. al,"Cache-Memory Interfaces in Compressed Memory Systems", IEEE Trans on Computers, Nov. 2001.
14) V.  Delaluz, et. al,"Hardware and Software Techniques for Controlling DRAM Power Modes ", IEEE Transactions on Computers, Nov. 2001.
15)V.  Krishnan et. al, " A Chip-Multiprocessor Architecture with Speculative Multithreading ", IEEE Transactions on Computers, Sept. 1999.
16) K. Lahiri,"Lotterybus: A New High-Performance Communication Architecture for Systems -on-chip Designs ",Design Automation Conference,2001.
 

B. RECONFIGURABLE ARCHITECTURES AND FAULT TOLERANT SYSTEMS

1) H. Zhang,"A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications", IEEE Journal on Solid State Circuits, Vol. 35, Nov 2000, pgs 1697-1704.
2) R. Maxion et. al,"Anomaly Detection in Embedded Systems", IEEE Transactions on Computers, Feb 2002, pgs 108-120.
3) Jiexo et. al,"Rigorous Development of an Embedded Fault- Tolerant System based on co-ordinated Atomic Actions", IEEE Transactions on Computers, Vol. 51, Feb 2002, pgs 164-
4) H. Singh et. al,"Morphosys: an integrated recounfigurable system for data parallel and computation intensive applications", IEEE Transactions on Computers, May 2000.
5) E. Sanchez et. al, "Static and Dynamic Configurable Systems",IEEE Transactions on Computers,June 1999.
6) S. Wiltonet et. al,"The Memory Logic Interface in FPGA's with large Embedded Memory Arrays", Transactions on VLSI, March 1999.
7) T. Miyazaki  " PROTEUS-lite project: dedicated to developing a telecommunication-oriented FPGA and its applications", IEEE Transactions on VLSI, Feb 2000.
8) A. Marquardt,"Speed and Area Tradeoffs in Cluster-Based FPGA Architectures", IEEE Transactions on VLSI, Feb. 2000. 
9) B. Salefski,"Re-Configurable Computing inWireless",Design Automation Conference, 2001.
 
 

C. ARCHITECTURES FOR MOBILE AND WIRELESS APPLICATIONS

1) Gonzales,"Micro-RISC Architectures for the Wireless Market", IEEE Micro, July-August 1999, pgs 30-37.
2) H. Takata et. al,"The D30V/MPEG Multimedia processor", IEEE Micro, July-August 1999, pgs 30-47.
3) H. Ikeda et. al," SuperENC: MPEG-2 Video Encoder Chip", IEEE Micro, July-August 1999, pgs 56-65.
4) H. Zhang et. al,"A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications",IEEE Journal on Solid State Circuits, Vol. 35, Nov 2000, pgs 1697-1704.
5) H-S. Chang et. al,"A Reed - Solomon product-code decoder chip for DVD applications", JSSC, Vol. 36, Feb 2001, pgs 229-238.
6) A. Abriat et. al,"A New Contactless Smart Card IC using an on-chip antenna and an asynchronous microcontroller", IEEE JSSC, Vol. 37, No. 7, July 2001, pgs 1101-1107.
7) W. Hinrichs et. al,"A 1-3 60PS Parallel DSP for High Performance Image Processing Applications", IEEE JSSC, Vol. 35, No. 7, July 2000, pgs 946-952.
8) S.B. Senthinathan et. al,"A 650 MHz, IA 32 microprocessor with enhganced data streaming for graphics and video", IEEE JSSC, Vol. 34, No. 11, Nov. 1999, pgs 1454-1465.
9) S. B. Park et. al,"A 0.25, 600 MHz, 1.5V fully depleted SOI 64 bit microprocessor", IEEE JSSC, Nov. 1999, pgs 1436-1445.
10) J. Kin,"Exploring the Diversity of Multimedia Systems", IEEE Transactions on VLSI, June 2001.
 
 

D. HIGH PERFORMANCE ARCHITECTURES

1) J. Choquette et. al,"High-Performance RISC microprocessors", IEEE Micro, July-August 1999, pgs 48-55.
2) N. Vasseghi, "200 MHz superscalar RISC microprocessor", IEEE Journal Solid-state Circuits, Vol. 31, pgs 1625-1685, Nov. 1996.
3) E. Waingold et. al,"Baring It All to Software: RAW Machines", IEEE Computer, 1997, pgs 06-93.
4) F. Behbahani et. al, "Adaptive Analog IF Signal Processor for a Wide-Band CMOS Wireless Receiver", IEEE JSSC, Vol. 36, No. 8, August 2001, pgs 1205-1217.
5) L. Clark et. al, "An embedded 32 bit microprocessor core for low-power and high-performance applications", IEEE JSSC, Nov. 2001, pgs 1599-1608.
6) A. Kowalczyk et. al,"The first MAJC  microprocessor: A dual CPU Systems-on-chip", IEEE JSSC, Vol. 36, Nov. 2001, pgs 1609-1616.
7) S. Rus et. al,"The first IA-64 microprocessor", IEEE JSSC, Vol. 35, Nov. 2000, pgs 1539-1544.
8) F. Karim,"On Chip Communication Architectures for OC- 768 Network Processors", DAC 2001.
9) D. Wingard,"Micro Network Based Integration for SOC",DAC,2001.
10) M. Sgroi et. al,"Addressing the SOC Interconnect Woes through communication based Design", DAC,2001.