VSD- LAB has the following on going research :

High-level synthesis and optimization of analog and mixed-signal systems

The goal of the research is to develop efficient methodologies and tools for automated synthesis of analog and mixed-signal systems from high level specifications (e.g., SystemC and VHDL-AMS). The motivation for high-level synthesis of analog and mixed-signal systems (AMS-HLS) is acheiving short design cycles with a reduced design effort and providing designs that are correct by construction. Our mixed-signal synthesis research addresses a top-down methodology.

In particular, we study the following topics:

Synthesis-oriented modeling of analog and mixed-signal systems.

Specification for synthesis of analog and mixed-signal sysems.

Performance model generation for time and frequency behavior.

Architecture (topology) generation techniques.

Parameter optimization techniques.

Design of reconfigurable Sigma-Delta modulators.

Graduate students

Hua Tang, Ph.D. candidate
Hui Zhang, Ph.D. candidate
Ying Wei, Ph.D. student
Gaurav Gothoskar, M.S. (graduated May 2002)

Funded by DARPA.Funding Period: September 1 2001 - May 31 2004.
Funded by NSF Center for Design of Analog and Digital Integrated Circuits (CDADIC).Funding Period: September 1 2004 - August 31 2005.

Relevant Publications

A. Doboli, N. Dhanwada, A. Nunez, R. Vemuri, "A Library-Based Approach to Synthesis of Analog Systems from VHDL-AMS Specifications", ACM Transactions on Design Automation, Vol. 9, Issue 2, pp. 238-271, April 2004.

H. Tang, H. Zhang, A. Doboli, "Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications - A Case Study for a Sigma-Delta Analog-Digital Converter", in C. Grimm, editor, "Languages for System Specification and Verification", Kluwer, 2004.

A. Doboli, R. Vemuri, "Exploration-Based High-Level Synthesis of Linear Analog Systems Operating at Low/Medium Frequencies", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 22, No. 11 2003.

A. Doboli, R. Vemuri, "Behavioral Modeling for High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS", IEEE Transactions on CADICS, Vol. 22, No. 11, 2003.

A. Doboli, R. Vemuri, "A Regularity-based Hierarchical Symbolic Analysis Method for Large-scale Analog Networks", IEEE Transactions on Circuits & Systems II, Vol. 48, No 11, pp. 1054-1067, November 2001.

SoC and Hardware Software Co-design

Our goal is to provide system-level methodologies and algorithms for designing highly constraint embedded SoC systems. Addressed methods include hardware-software partitioning, task scheduling, and bus architecture synthesis. We target applications that include a significant amount of data and control dependencies. Addressed performance constraints include speed, silicon area and consumed power. We also study modeling of layout aspects for system design, such as substrate coupling and bus parasitic.

In particular, we study the following topics:

IP core integration, including bus architecture synthesis, arbiter design and buffer sizing.

Stochastic modeling for embedded system design, e.g., arbiter design.

Substrate coupling for mixed-signal SoC, including digital noise macromodeling and simulation.

Hardware-software co-design algorithms, such as combined partitioning and scheduling, and awarness to lower design levels.

Graduate students

Nattawut Thepayasuvam, Ph.D. candidate
Sankalp Kallakuri, Ph.D. candidate
Yulei Weng, Ph.D. candidate
Vaishali Damle, M.S. graduated in December 2003
Rohit Pai, M.S., graduated in December 2003

Funded by a DAC Graduate Scholarship Award. Funding Period: September 1 2001 - August 30 2003.
Funded by an IBM Faculty Partnership Award. Funding Period: September 1 2001 - December 1 2002.
Funded by NY State Center for Advanced Technologies in Sensor and Diagnostic Tools. Funding Period: Summer 2003, Summer 2004.
Funded by Microsoft. Funding Period: January 2004-December 2004.

Related Publications

N. Thepayasuwan, A. Doboli, "Layout Conscious Approach and Bus Architecture Synthesis for Hardware-Software Co-Design of Systems on Chip Optimized for Speed", accepted for publication, IEEE Transactions on VLSI Systems, 2004.

N. Thepayasuwan, A. Doboli, "Pruning-based Synthesis of Flat and Hierarchical Bus Architectures for SoC in Deep Submicron Technologies", International Journal on Embedded Computing, Vol. 1, 2004.

N. Thepayasuwan, A. Doboli, ``Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip'', Design, Automation and Test in Europe Conference (DATE) 2004, Paris.

S. Kallakuri, A. Doboli, S. Doboli, "Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies", International Symposium on VLSI (ISVLSI), 2004.

N. Thepayasuwan, V. Damle, A. Doboli, ``Bus Architecture Synthesis for Hardware-Software Co-Design for Deep Submicron Systems on Chip'', International Conference on Computer Design (ICCD) 2003, San Jose CA.

A. Doboli, "Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design of Embedded Systems under Power and Latency Constraints", Proceedings of the Design, Automation and Test in Europe Conference, 2001, Munich.

Design Automation for Sensor Network Applications

Graduate students

Sankalp Kallakuri, Ph.D. candidate
Yulei Weng, Ph.D. candidate
Yang Zhang, Ph.D. student

Funded by NY State Center for Advanced Technologies in Sensor and Diagnostic Tools. Funding Period: Summer 2003, Summer 2004.

Related Publications

Y. Weng, A. Doboli, ``Smart Sensor Architecture Customized for Image Processing Applications'', Proc. 10th IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, Toronto.

Y. Weng, S. Kallakuri, A. Doboli, ``Dynamic Architecture Adaptation to Improve Scalability of Sensor Networks: A Case Study for a Smart Sensor for Face Recognition'', accepted for publication, Work in Progress Section, Real Time System Symposium (RTSS), 2004, Lisbon.