Modeling Process Parameter Variations in Analog Circuits

This project has been developing a scalable method (called ALAMO) for comprehensively modeling the influence of MOSFET process parameter variations on analog circuit performance.


The method expresses all device parameter variation constraints extracted from the circuit layout, including:

1. Process/model parameter variation of individual devices, and

2. Mismatch of process/model parameters of device pairs.


The method calculates specific process/model parameter values for each MOSFET in an analog circuit using as inputs:

 A set of constraints defining the process parameter variances of individual devices and the process parameter covariance of device pairs, and

 The circuit layout.


The method relies on the same representation as s-space method, however, it captures not only the mismatch of process/model parameters (like in s-space method), but also the process parameter variations of individual devices in a circuit.


As the resulting circuit descriptions might be too complex to calculate and simulate, the method uses layout regularity analysis (LRA) and principal equation analysis (PEA) to reduce the complexity of the models. LRA reduces the number of unknowns involved in the models by finding devices and device pairs with similar statistical behavior. PEA reduces the number of relationships that link the stochastic model parameters by eliminating less important parameter correlations. Elimination uses sensitivity-based priorities that are attached to each relationship between device parameters, and an error function to estimate the total approximation error.

Latch-type SRAM sense amplifier

Latch-type SRAM sense amplifier yield vs. input voltage difference

MC analysis for the latch-type SRAM sense amplifier design underestimates the IC yield (figure above), and overestimates the sensing delay by about 80%, the total delay by about 58%, and the offset input voltage difference by about 40%.


Experiments show that ALAMO method is more accurate than Monte-Carlo (MC) and s-space methods, and scales well even for large analog circuits. MC analysis can be imprecise. It overestimated by large amounts, between 40%-80% in our experiments, the impact of MOSFET mismatch on circuit performance. Similarly, s-space method did not produce accurate results for circuit performance (e.g., differential node gain, input voltage swing, harmonic distortion, etc.) that also depends on the parameter variation of individual MOSFET devices. In contrast, our methodology generated correct results. It is also effective in reducing the modeling problem complexity: the number of eliminated modeling variables was between 34%-94%, and the number of eliminated modeling equations was between 76%-99.5%. This reduced the modeling time by more than 70% without significantly influencing accuracy.


ALAMO, our method, is useful for post-layout verification during analog circuit design and synthesis. Given a circuit layout, the method computes customized process models for each device in the layout to include the effects of process parameter variations. Then, using the customized process models, the extracted circuits are simulated using commercial simulators, like SPICE or Spectre. The method is also useful to estimate the quality of a layout style, e.g., stacked, common centroid, etc, for a given performance specification.



Related Publications


H. Zhang, A. Doboli, "A Scalable Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits", Microelectronics Journal, Elsevier, Volume 38, Number 12, December 2008.