ESE555 VLSI Circuit Design

Fall 1997

Instructor: Brad Carlson, Associate Professor
Office: 215 Light Engineering
Phone: 632-8474
Fax: 632-8494
Email: bcarlson@jessica.ee.sunysb.edu
http://www.ee.sunysb.edu/~bcarlson/bcarlson.html
Office hours: 4:00-6:00pm Monday and Tuesday
Class hours: 7-10pm Monday
Classroom: 154 Light Engineering
Computer lab: 112 Old Engineering
Computer lab hours: TBD

Grades

IMPORTANT ANNOUNCEMENTS:

• The first class meeting is September 15.
  
• You can begin working on the CAD tool tutorials by access the Getting started tutorial. You can get a computer account from Mr. John Milazzo in room 112 of Old Engineering provided you are officially registered for the course.
  
• The class scheduled for September 8 is cancelled.
  
• The lecture on October 13 is cancelled.
  
• Homework 2 is due on October 13, and homework 3 will be available on October 13.
  
• The lecture on November 3 is NOT cancelled, and will be covered by one of my graduate students.
  
• Refer to http://www.ee.sunysb.edu/~bcarlson/schedule.html for my travel schedule.
  
• A description of this course can be found in the following paper.
  B.S. Carlson, "A VLSI Circuit Design Course for Practitioners and Researchers," in Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1997. (paper, poster)

Text Book:

N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd Edition, Addison-Wesley, 1993.

Supplements:

R. Lipsett, et.al., VHDL: Hardware Description and Design, Kluwer, 1989.

J.P. Uyemura, Circuit Design for CMOS VLSI, Kluwer, 1992.

Reference Books: (On reserve in the electrical engineering and/or computer science library.)

N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1985.

L. Glasser and D. Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley, 1985.

Course Outline:

1. Introduction to CMOS Circuits
   1. Design of primitive gates
   2. Design of complex gates
2. Review of MOS Transistor Theory
   1. nMOS and pMOS enhancement transistors
   2. DC characteristics of CMOS inverter
   3. DC characteristics of transmission gate
   4. Latch-up
3. CMOS Processing Technology
   1. CMOS technologies
      1. p-well and n-well processes
      2. Twin tub process
      3. Silicon on insulator
   2. Layout Design Rules
4. Circuit Characterization
   1. Resistance estimation
   2. Capacitance estimation
   3. Switching characteristics
   4. Transistor sizing
   5. Power consumption
   6. Charge sharing
   7. Scaling of MOS transistor dimensions
5. Schematic Capture
   1. Design entry
   2. Simulation
   3. Synthesis
6. Hardware Description Languages
   1. Behavioral descriptions
   2. Structural descriptions
   3. VHDL
   4. Simulation
   5. Synthesis
7. CMOS Circuit and Logic Design
   1. CMOS logic structures
   2. Electrical and physical design of logic gates
   3. Clocking strategies
   4. Input-output structures
8. System Design
   1. Structured design and testing
   2. Typical design cycle
   3. Symbolic layout systems
   4. CMOS subsystem design
      1. Adders, multipliers, counters, shift registers
      2. Random access memories
      3. Static RAM cell
      4. Dynamic RAM cell
      5. Programmable logic arrays
9. ASIC Design
10. BiCMOS Circuit Design
11. Introduction to Analog CMOS IC Design

Homework:

Each homework assignment will require a final report, and the computer files pertinent to each assignment must be accessible by the instructor. Hand written reports are not acceptable. The homeworks and project will be performed using computer-aided design software on UNIX^TM workstations. The students are responsible for learning to use the operating system and the software with the assistance of tutorials, class handouts and the professor. You are strongly encouraged to obtain a general purpose computer account for the HP-UNIX system from Instructional Computing. If you have never used the UNIX operating system, then it is suggested that you spend the first two weeks of this course familiarizing yourself with it. There are numerous books available in local book stores.

Homework Schedule
	Date assigned	Date due
Homework 1	Sep. 15	Sep. 29
Homework 2	Sep. 29	Oct. 13
Homework 3	Oct. 13	Nov. 3
Project	Nov. 3	Dec. 8

Exams:

Each exam will be three hours in duration, and their scopes will be topics discussed during the lectures.

Exam Schedule
	Date
Exam 1	Oct. 27
Exam 2	Dec. 15

Grading:

Assignment	Weight
Homework 1	14%
Homework 2	14%
Homework 3	14%
Project	28%
Exam 1	15%
Exam 2	15%

The final class meeting is Dec. 8, and exam 2 will be given during the regularly scheduled final exam period on Dec. 15 from 7-10 pm.

If you have a physical, psychological, medical or learning disability that may impact on your ability to carry out assigned course work, I would urge that you contact the staff in the Disabled Student Services office (DSS), Room 133 Humanities, 632-6748/TDD. DSS will review your concerns and determine, with you, what accommodations are necessary and appropriate. All information and documentation of disability is confidential.