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Mikhail Dorojevets Associate Professor
Department of Electrical & Computer Engineering
State University of New York
Stony Brook, NY 11794-2350
Phone: (631) 632-8611
Fax: (631) 632-8494
- parallel computer architectures, multithreading
- high-performance processor and system design
energy-efficient superconductor processors
US patent 7,196,708 (with Eiji Ogura) “Parallel vector
One US patent pending.
Short Biography Mikhail Dorojevets received his M.S. degree in Physics and Electronic Engineering from the Institute of Physics and Technology, Moscow in 1982. He received his Ph.D. degree in Computer Engineering from the Russian Academy of Sciences in 1988. From 1982 to 1995, he was a principal designer in several projects on high-performance systems design for Russian science, defense, and industry. For his work on the MARS-M supercomputer with decoupled multithreaded architecture built by 1988, he received the Outstanding Achievement Diploma jointly awarded by the USSR Academy of Sciences, and the USSR State Committee on Science and Technology. Since 1996, he has been an Assistant and (since 2000) an Associate Professor of the Department of Electrical and Computer Engineering, at Stony Brook
University (SBU). His research interests include parallel computer architectures, and all aspects of microprocessor and computer design.
In 1997-2001, he developed a novel multithreaded SPELL architecture for
the HTMT petaflops computer project and the microarchitecture of an experimental 20 GHz superconductor FLUX processor in projects sponsored by
US DoD and NASA.
2003-2004, he was an architect of a scalable video platform architecture for
video processors for Sony Electronics, Inc. (San Jose, CA). In 2008-2011, he
was an architect and principal logic cell-level designer of a superconductor
GHz Frontier processor datapath using Hypres' 4.5 kA/cm2 NB-trilayer
technology in a joint project with Hypres, Inc (Elmsford, NY) sponsored by US
ARO. The major datapath component - a 8-bit ALU with ~ 8K Josephson
junctions (JJs), was successfully designed, fabricated, and demonstrated complete
operation at 20 GHz in April 2011. Since 2010, Mikhail Dorojevets and his design
team at Stony Brook have been working on the architecture and complete logical
and physical layout design of a 30 GHz 16-bit RSFQ processor implemented
with ISTEC 1.0 µm
10 kA/cm2 superconductor technology in a joint project with
colleagues at the the National Universities of Yokohama and Nagoya (Japan).
In 2011, the world's first 16-bit
wave-pipelined RSFQ parallel-prefix sparse-tree adder with ~ 10K JJs a 30-GHz target clock frequency
was designed by Mikhail Dorojevets and Chris L. Ayala at Stony Brook University using the Japanese CONNECT cell
library, fabricated, and successfully tested at low
frequency by the SBU team with assistance of the colleagues from the National
University of Yokohama. In 2012, the first 8x8-bit parallel carry-save RSFQ
multiplier with 6240 JJs and the maximum frequency of 20 GHz was designed by
Mikhail Dorojevets and Artur. K. Kasperek at SBU using the CONNECT cell library, fabricated,
and successfully tested at low frequency for the vast majority of test vectors.
Mikhail Dorojevets's current research work is focused on the development of
energy-efficient superconductor processors with ultra-low-power consumption. Since 2004, Mikhail Dorojevets has been a
Department of Defense
Superconducting Technology Assessment Panel.
Department of Electrical & Computer Engineering | Computer Engineering | Stony Brook