ESE 345: Computer Architecture
Spring 2024
Description: This course focuses on the fundamental techniques of designing and evaluating modern computer architectures and tradeoffs present at the hardware/software boundary. The emphasis is on instruction set design, processor design, memory and parallel processing. Students will undertake a design project using a hardware description language and modern CAD tools.
Prerequisites: ESE 280 and ESE 382 3 credits
Instructor: Prof. Mikhail Dorojevets
Office: 243 Light Engineering, 632-8611
Office Hours: M 10:00 am -12:00 pm
E-mail: mikhail.dorojevets@stonybrook.edu
Lecture: MW 5:30-6:50 PM 152 Light Eng.
Course website: http://www.ece.stonybrook.edu/~midor/ESE345/index.html
The last lecture slides (pdf) are here. (If necessary, use "Open link in new window" to see and save the slides).
Teaching Assistants:
Ramisa Fatima
Email: ramisa.fatima@stonybrook.edu TA hours: Tuesday Thursday 1:00 - 2:00 pm
Textbook: David A. Patterson and John L. Hennessy. Computer Organization &
Design The Hardware/Software Interface, Sixth Edition by David A. Patterson
and John L. Hennessy, 2021 by Elsevier Inc. ISBN:978-0-12-820109-1
Recommended Books on the VHDL:
1. Peter J. Ashenden. The Designer’s Guide to VHDL, 3rd edition, Morgan Kaufmann Publishers, 2008,
ISBN: 978-0-12-088785-9.
Course Grading: Homeworks: 12% (submission during TA hours)
Exams: (two in-class midterms): 66%
Project: 22%
Submissions of both midterms & project are required for every student in this class!
Project Part 1 (VHDL ALU functions) Deadline: 11:59 PM March 29, 2024 by email to TA Ramisa Fatima and Instructor
Full Project Deadline: 1:00 PM April 28, 2024 by email to TA Ramisa Fatima and Instructor
Project Presentations: April 29 - 30, 2024 (TBA)
Course Learning Outcomes:
Upon completion of this course, students will learn: 1) computer performance and instruction set design principles, 2) MIPS architecture and basics of assembly language programming, 3) integer and floating-point arithmetic, 4) processor, caches, and memory design, and 5) use of VHDL/Verilog languages in the processor datapath design and verification.