• The homework asked you to design master-slave D flip flop follow these schematics in the book (see HW description for details):

     The clock input can be a different metal layer (eg. m2) from the rest of routing metal layer(eg. m1)

• An example D flip flop layout using different schematic is shown below for your reference.

     Your design is much smaller than this one because of different schematics we choose.

     For more details of the layout below you can go to:

     http://www.engr.sjsu.edu/~dparent/ee166

• TSMC standard cell library, more digital cell layout examples.