FAQ

   1. how to design the DFF?

 2. how to set the input signal for simulation?

• The homework asked you to design master-slave D flip flop following Figure 7.7, 7-10 in the book.
• Alternatively, you can use the following schematic with less transistors for DFF design.

     The clock input can be a different metal layer (eg. m2) from the rest of routing metal layer(eg. m1)

• To get familiar with layouts, an example D flip flop layout using different schematic is shown below for your reference. This layout has two metal layer, m1 (blue) for basic routing and m2(pink) for signal routing.

    Your layout can be even smaller than this one if you choose the schematics in the book or above. Make sure your layout follows the style below so that your design can be as compact as possible. In general the cells should share the same VDD/GND line and should be placed as close to each other as possible. 

     For more details of the layout below you can go to:

     http://www.engr.sjsu.edu/~dparent/ee166

• TSMC standard cell library, more digital cell layout examples.

• Input setup:

   To simulate the DFF, there are two inputs, D and CLK needed to be set. You can set   CLK to a period of T and D to 2T in order to show out put flips according to the CLK and D.

    One example input setup for Hspice is shown in Notes for HW2.  .