ESE355 Lab - Project
Homework Description (See handouts)
The IR queue and IR block gate level
design discussed in the lab is posted here.
You can make modifications based on this
IR example according to your own need for more/less control signals.
Standard Cells
- A 3-state buffer cell is added to ~ee355/vsclib, filename:
buff121.mag. This one seems working well, use it if you don't have your own 3-state buffer.
- A D flip-flop is created by TA. The file is ~ee355/dff311.mag. Please note this cell is not fully tested,
I suggest you use your own DFF from HW2 because it is from the same
technology.
- The standard cell library is in ~ee355/vsclib. This is all we have. If you want something like 8 to 1 Mux, you need build them by yourself BASED ON the cells in this library.
- The cell sharing between different groups must be limited to some basic function blocks such as D flip-flop, 1-bit adder, 8-to-1 Mux, buffer and so on.
- The document of standard cell library is online:
at www.vlsitechnolog.org.
- Check .sim files to see what nets you have before doing simulation.you might set not only
vss but also GND to low.
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Pad Frame new!
- Check the pad frame file /user3/ee355/pad_frame/SBFrame.mag
- The pad frame has 40 pads. 2 pads for VDD and GND, the rest 38 pads are bi-direction pads. You can set "OEB" as high or low to config this type of pad as an input or output pad. Check the document (.pdf file) in pad_frame directory.
- The number of pads are less than the total number of input/output signals. You will have to share some pads when load instructions or transmit data between the processor and memories.