Course Instructor: Dr. Shan Lin
Department of Computer and Information Science, Temple University
Home | Overview | Textbook | Grading | Mandatory Prerequisites |
This course will introduce computer architecture and organization with an emphasis on the parallel and modern microprocessors. This course will cover the fundamentals of processor core, the memory system, and design issues when we interconnect them to build a multiprocessor system. The course material is drawn from textbooks as well as classic papers from computer architecture conferences and journals.
This course will cover the following topics:
Basics of pipelining | |
Hazards and exceptions | |
Multi-cycle pipelines and implementing precise interrupts | |
Superscalar processor design | |
– Fetch and decode issues; branch prediction – Register renaming – Dynamic instruction scheduling – Load/store unit design and memory dependence prediction |
|
Memory-system design | |
– Basics of caches, virtual memory, and main-memory design – Victim caches, prefetching, and stream buffers |
|
Multiprocessor concepts | |
– Multiprocessor taxonomy and communication models – Coherence and consistency |
|
Storage system | |
Networked and embedded system |
Required Textbook:
J. L. Hennessy and D. A. Patterson, “Computer
Architecture: A Quantitative Approach”, Fourth Edition,Morgan Kaufmann.
Supplemental Textbook:
D. A. Patterson and J. L. Hennessy's "Computer
Organization and Design: The Hardware/Software Interface", Elsevier/Morgan
Kaufmann.
J. P. Shen and
M. H. Lipasti, “Modern Processor Design”, First Edition, McGraw-Hill.
Homework 30%
Midterm 30%
Final Project 40%
This course on computer architecture assumes prior knowledge of computer organization and architecture. You should already be familiar with hardware basics, instruction set architecture, pipelines, computer arithmetic, and digital logic. Students will have expected to have had a course that covers the material in a textbook/course such as Patterson and Hennessy's "Computer Organization and Design: The Hardware/Software Interface".
This page was last modified on 02/12/2013[home]