FALL 2001
ESE 549: Digital Systems Testing

 


Instructor: Prof. Sangjin Hong
Office: 217 Light Engineering Building
E-mail: snjhong@ece.sunysb.edu

General Information

Prerequisite: TBD
Time and Place: TBD
Teaching Assistants: TBD
Textbook: TBD
References: TBD

Course Goals

This course examines in depth the theory and practice of fault analysis, test generation, and design for testability for digital integrated circuits and systems. The topics to be covered include: circuit and system modeling; fault sources and types; the single stuck-line fault model; fault simulation methods; test generation algorithms for combinational and sequential circuits, including PODEM; testability measures; design-for-testability techniques; scan design; test compression methods; logic-level diagnosis; self-checking circuits; built-in self-testing (BIST); system-level diagnosis; processor and memory testing; VLSI and system-on-a-chip (SOC) testing; design verification and its relation to physical fault testing. A term paper or small experimental/research project will be part of the course.

Topical Outline

1.

TBD

Hours: TBD

TBD

2. TBD Hours: TBD

TBD

3. TBD Hours: TBD

TBD

Grading

The grade will be based upon:
    (1) Homeworks (30%)
    (3) Exams (70%) (Midterm1 20%, Midterm2 20%, Final 30%)

Announcements

1/25 NO LECTURE ON Feb. 1.

Spring 2001 Tentative Schedule
Week
Lecture
Tuesday
Lecture
Thursday
Topics Lab Textbook
Reading
Jan. 22 -
Jan. 26
no lecture
lecture 1
homework 1
number systems,
logic symbols
no lab
1-1, 1-2, 1-3,
1-4, 1-5
Jan. 29 -
Feb. 2
lecture 2
no lecture
no office hours
Boolean algebra
no lab
2-1, 2-2, 2-3
Feb. 5 -
Feb. 9
lecture 3
hw1 sol., homework 2
lecture 4
logic minimization,
Karnaugh Map
lab 1
familiarization 1
2-4, 2-5, 2-6,
2-7, 2-8
Feb. 12 -
Feb. 16
lecture 5
hw 2 sol, homework 3
lecture 6
combinational
logic design
lab 2
familiarization 2
3-3, 3-4, 3-5,
3-6, 3-7
Feb. 19 -
Feb. 23
lecture 7
hw 3 sol, homework 4
lecture 8
design examples:
adder, subtractor
lab 3
combinational logic
3-8, 3-9, 3-10,
3-11, 3-12
Feb. 26 -
Mar. 2
lecture 9
hw 4 sol
midterm 1 solution
review
no lab

Mar. 5 -
Mar. 9
lecture 10
homework 5
lecture 11
state elements:
latches, flip-flops
lab 4
Iterative networks
4-1, 4-2, 4-3
Mar. 12 -
Mar. 16
lecture 12
hw 5 due, homework 6
lecture 13
sequential circuits,
sequence detector
lab 5
state elements
4-4, 4-5
Mar. 19 -
Mar. 23
Spring
Recess
Spring
Recess
Spring
Recess
Spring
Recess
Spring
Recess
Mar. 26 -
Mar. 30
lecture 14
hw 6 due, homework 7
lecture 15
design examples:,
sequence detectors
lab 6
sequence detector
4-6, 4-7
Apr. 2 -
Apr. 6
lecture 16
hw 7 due, homework 8
lecture 17
registers
counters
lab 7
finite state machine
5-1, 5-2, 5-3
Apr. 9 -
Apr. 13
lecture 18
hw 8 due, homework 9
lecture 19
design examples:
binary counters
lab 8
shifter and counter
5-4, 5-5
Apr. 16 -
Apr. 20
lecture 20
hw 9 due
midterm 2
review
no lab

Apr. 23 -
Apr. 27
lecture 21
homework 10
lecture 22
buffer, memory
lab 9
multiplier
6-1, 6-2, 6-3
Apr. 30 -
May 4
lecture 23
hw 10 due, homework 11
lecture 24
RAM, ROM
lab 10
logic with memory
6-4, 6-5, 6-6,
6-7, 6-8
May 7 -
May 11
lecture 25
hw 11 due
no lecture
datapath
no lab
7

Last updated on: 1 January, 2001