FALL 2009
ESE 555: Advanced VLSI System Design

 

Instructor: Prof. Sangjin Hong
Office: 217 Light Engineering Building
Office Hours: TW 1:45 p.m. - 3:45 p.m.
E-mail: snjhong@ece.sunysb.edu

General Information

Prerequisite: ESE 318 and ESE 330 or equivalent. Students are expected to know the logic design, circuits and device physics, and electronic design automation tools. Some background in computer architecture is helpful, but not required.
Time and Place: Th 12:30pm. - 3:30p.m. in Room 124 Chemistry Building
Teaching Assistants: No TA is available
Textbook: Digital Integrated Circuits by Rabaey
CMOS VLSI Design by Weste

Course Goals

Advanced very large scale integration (VLSI) circuit design. Design methodologies (architectural simulation, hardware description language design entry, silicon compilation, and verification), microarchitectures, interconnect, packaging, noise sources, circuit techniques, design for testability, design rules, VLSI technologies (silicon and GaAs), and yield. Projects in chip design.

Project

This is a project-oriented course in which you will design a modest-sized CMOS integrated circuit. No specific lab times are scheduled, and you can work at your convenience. Graduate Student Computer Lab is open 24 hours a day. You need to get a key card from the department. Integrated circuit design is mastered only through experience. The CAD assignments, as well as lectures, will be closely ties to the final project, the design of a simple RISC microprocessor. The design of cells for the project will be done in a group of 2-3. Each group will receive same grade for the project. The final project must be completed, and you must submit a final report. Within the constraints of available funding, eligible projects will be fabricated through the MOSIS service.

Grading

The grade will be based upon:
    (1) CAD Assignments (40%) (No late CAD assignment)
    (2) Demo and Final Report (20%)
    (3) Exams (40%) (Midterm1 20%, Midterm2 20%)

Handouts

(1) Project Description
(2) Cadence Tutorial (for CAD Assignment 1)
(3) MOSIS Scalable CMOS Design Rule (Short Version)
(4) More to come...

Project Groups

Group 1:
Group 2:
Group 3:
Group 4:
Group 5:
Group 6:

Announcements

9/3 Cad Assignment #1 Due September 17.
9/3 cshrc.cadence
9/17 Cad Assignment #2 Due October 6.
9/24 Cad Assignment #3 Due October 15.
9/24 Midterm #1 is Scheduled on October 22.
10/6 Cad Assignment #4 Due October 29.
11/5 Cad Assignment #5 Due November 12.
11/5 Cad Assignment #6 Due November 19.
11/5 Cad Assignment #7 Due December 3.
11/5 Midterm #2 is Scheduled on December 10.


Last updated on: 1 September, 2006