SPRING 2015
ESE 575: Advanced VLSI Signal Processing Architectures

 

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Instructor: Prof. Sangjin Hong
Office: 201 Light Engineering Building
E-mail: snjhong@ece.sunysb.edu

01

General Information

Prerequisite: TBD
Time and Place: Th 4:00-7:00 p.m. 124 Chemistry Building
Textbook: K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley and Sons, 1999.
References: P. Pirsch, Architecture for Digital Signal Processing, John Wiley and Sons, 1998.

Course Descriptions

This course is concerned with advanced aspects of VLSI architecture in digital signal proc essing and wireless communications. The first phase of the course covers the der ivation of both data transformation and control sequencing from a behavioral des cription of an algorithm. The next phase reviews the general purpose and dedicat ed processor for signal processing algorithms. This course focuses on low-comple xity high-performance algorithm development and evaluation, system architecture modeling, power-performance tradeoff analysis. The emphasis is on the developmen t of application-specific VLSI architectures. An advanced experimental/research project is required.

Topical Outline

1.

DSP Algorithm Design

Hours: TBD

DSP representations (data-flow, control-flow, and signal-flow graphs, block diagrams), fixed-point DSP design (A/D precision, coefficient quantization, round-off and scaling), filter structures (recursive, non-recursive and lattice), algorithmic simulations of DSP systems in C and MATLAB, behavioral modeling in VHDL.

2. Circuits and DSP Architecture Design Hours: TBD

Fast filtering algorithms (Winograd's, short-length FIR), retiming and pipelining, block precessing, folding, distributed arithmetic architectures, VLSI performance measures (area, power, and speed), structural modeling in VHDL.

3. DSP Module Synthesis Hours: TBD

Arithmetic unit architectures (adders, multipliers, dividers), bit-parallel, bit-serial, digit-serial, carry-save architectures, redundant number system, modeling for synthesis in VHDL, synthesis via SYNOPSYS, place-and-route via CADENCE.

Grading

The grade will be based upon:
    (1) Midterm Exam (TBD%)
    (2) Final Exam (TBD%)
    (3) Final Project (40%)

Handouts

(1) Syllabus


Last updated on: 14 January, 2015