ESE 575: Advanced VLSI Signal Processing
Selected Reading List
Low Power Design
1. A. P. Chandrakasan, S. Sheng, R. W. Brodersen, "Low-Power CMOS Digital Design,"
IEEE Journal of Solid-State Circuits, vol. 27, no. 4, April 1992.
2. A. P. Chandrakasan, R. W. Brodersen, "Minimizing Power Consumpsion in Digital CMOS Circuits," Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, April 1995.
3. B. Sklar, "Defining, Designing, and Evaluating Digital Communication Systems,"
IEEE Communications Magazine, vol. 31, no. 11, pp. 91-101, November 1993.
4. R. Prasad, T. Ojanpera, "An Overview of CDMA Evolution Toward Wideband CDMA,"
IEEE Communications Surveys, vol. 1, no. 1, pp. 2-29, 1998.
5. B. Sklar, "A Structured Overview of Digital Communications - A Tutorial Review-
Part I," IEEE Communications Magazine, August 1983.
6. J.M. Cioffi, V. Oksman, J.-J. Werner, T. Pollet, P.M.P. Spruyt, J.S. Chow,
K.S. Jacobsen, "Very-high-speed digital subscriber lines," IEEE Communications
Magazine, vol.37, no.4, p.72-79, April 1999.
7. P.S. Chow, J.M. Cioffi, J.A.C. Bingham, "DMT-based ADSL: concept, architecture,
and performance," IEE Colloquium on 'High Speed Access Technology and Services,
Including Video-on-Demand,' p.3/1-6, London, UK, 19 Oct. 1994.
8. V. B. Lawrence, L.J. Smithwick, J.-J. Werner, N. Zervos, "Broadband Access
to the Home on Copper," Bell Labs Technical Journal, Summer 1996.
9. A. O’Rourke, G. Ungerboeck, R. Joshi, D. Jones, "VDSL White Paper," Broadcom
10. B. Daneshrad, H. Samueli, "Finite wordlength requirements for adaptive
signal processing elements in digital QAM ADSL systems," Proceedings of ICC/SUPERCOMM'94
- 1994 International Conference on Communications, vol. 2. pp.838-842, New Orleans,
LA, 1-5 May 1994.
11. VDSL Coalition, http://www.vdsl.org
12. VDSL Alliance, http://www.vdslalliance.com
13. M. Hatamian, et al, "Design considerations for gigabit Ethernet 1000Base-T
twisted pair transceivers," Proceedings of the IEEE 1998 Custom Integrated Circuits
Conference, pp.335-342, Santa Clara, CA, 11-14 May 1998.
14. E.F. Haratsch, K. Azadet, "A low complexity joint equalizer and decoder
for 1000Base-T Gigabit Ethernet," Proceedings of the IEEE 2000 Custom Integrated
Circuits Conference, pp. 465-468, Orlando, FL, 21-24 May 2000.
15. K. Azadet, M.-L. Yu, P. Larsson, D. Inglis, "A gigabit transceiver chip
set for UTP CAT-6 cables in digital CMOS technology," 2000 IEEE International
Solid-State Circuits Conference. Digest of Technical Papers, p.306-307. 496,
San Francisco, CA, 7-9 Feb. 2000.
DSP Arithmetic and Transformations
16. P.M. Kogge, H.S. Stone, "A parallel algorithm for the efficient solution of
a general class of recurrence equations," IEEE Transactions on Computers, vol.
C-22, no. 8, pp. 786-793, August 1973.
17. A. Avizienis, "Signed-digit number representations for fast parallel arithmetic,"
IRE Transactions on Computers, September 1961.
18. R. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer-aided design system
for high performance FIR filter integrated circuits," IEEE Transactions on Signal
Processing, vol.39, no.7, pp.1655-1668, July 1991.
19. R.A. Hawley, B.C. Wong, T.-J. Lin, J. Laskowski, H. Samueli, "Design techniques
for silicon compiler implementations of high-speed FIR digital filters," IEEE
Journal of Solid-State Circuits, vol.31, no.5, pp.656-667, May 1996.
20. C.S.H. Wong, J.C. Rudell, G.T. Uehara, P.R. Gray, "A 50 MHz eight-tap adaptive
equalizer for partial-response channels," IEEE Journal of Solid-State Circuits,
vol.30, no.3, pp.228-234, March 1995.
21. L.E. Thon, P. Sutardja, F.-S. Lai, G. Coleman, "A 240 MHz 8-tap programmable
FIR filter for disk-drive read channels," 1995 IEEE International Solid-State
Circuits Conference. Digest of Technical Papers ISSCC '95, pp.82-3, 343, San
Francisco, CA, USA, 15-17 Feb. 1995.
22. D. Moloney, J. O'Brien, E. O'Rourke, F. Brianti, "Low-power 200-Msps, area-efficient,
five-tap programmable FIR filter," IEEE Journal of Solid-State Circuits, vol.33,
no.7, pp.1134-1138, July 1998.
23. R. B. Staszewski, K. Muhammad, P. Balsara, "A 550-MSample/s 8-Tap FIR Digital
Filter for Magnetic Recording Read Channels," IEEE Journal of Solid-State Circuits,
vol. 35, no. 8, pp. 1205-1210, August 2000.
24. K. Azadet, C.J. Nicole, "Low-power equalizer architectures for high speed
modems," IEEE Communications Magazine, vol.36, no.10, p.118-126, Oct. 1998.
25. P.J. Black, T.H. Meng, "A 140-Mb/s, 32-state, radix-4 Viterbi decoder," IEEE
Journal of Solid-State Circuits, vol.27, no.12, pp.1877-1885, Dec. 1992.
26. P.J. Black, T.H.-Y. Meng, "A 1-Gb/s, four-state, sliding block Viterbi decoder,"
IEEE Journal of Solid-State Circuits, vol.32, no.6, pp.797-805, June 1997.
27. G. Fettweis, H. Meyr, "Parallel Viterbi algorithm implementation: breaking
the ACS-bottleneck," IEEE Transactions on Communications, vol.37, no.8, p.785-90,
28. G. Fettweis, H. Meyr, "High-rate Viterbi processor: a systolic array solution,"
IEEE Journal on Selected Areas in Communications, vol.8, no.8, pp.1520-34, Oct.
29. G. Fettweis, H. Meyr, "High-speed parallel Viterbi decoding: algorithm and
VLSI-architecture," IEEE Communications Magazine, vol.29, no.5, pp. 46-55, May
30. A.K. Yeung, J.M. Rabaey, "A 210 Mb/s radix-4 bit-level pipelined Viterbi
decoder," 1995 IEEE International Solid-State Circuits Conference, Digest of
Technical Papers, ISSCC '95, pp.88-9, 344, San Francisco, CA, 15-17 Feb. 1995.
31. G. Fettweis, R. Karabed, P.H. Siegel, H.K. Thapar, "Reduced-complexity Viterbi
detector architectures for partial response signalling," Proceedings of GLOBECOM
'95, Singapore, vol.1, pp.559-563, 13-17 Nov. 1995.
32. T. Conway, "Implementation of high speed Viterbi detectors," Electronics
Letters, vol.35, no.24, pp.2089-2090, 25. Nov. 1999.
33. C.B. Shung, P.H. Siegel, G. Ungerboeck, H.K. Thapar, "VLSI architectures
for metric normalization in the Viterbi algorithm," IEEE International Conference
on Communications ICC '90, Atlanta, GA, pp.1723-1728, vol. 4, 16-19 April 1990.
34. A.P. Hekstra, "An alternative to metric rescaling in Viterbi decoders,"
IEEE Transactions on Communications, vol.37, no.11, p.1220-1222, Nov. 1989.
Programmable Digital Signal Processors
35. E.A. Lee, "Programmable DSP architectures. I," IEEE ASSP Magazine, vol.5,
no.4, pp.4-19, Oct. 1988.
36. E.A. Lee, "Programmable DSP architectures. II," IEEE ASSP Magazine, vol.6,
no.1, pp.4-14, Jan. 1989.
37. A. Gatherer, T. Stetzler, M. McMahan, E. Auslander, "DSP-based architectures
for mobile communications: past, present and future," IEEE Communications Magazine,
vol.38, no.1, pp.84-90, Jan. 2000.