ESE 318 Digital Systems Design
Instructor: Dr. Alex Doboli
Office
Hours:
Class
Material:
-
Text Book:
John Yarbrough, Digital Logic – Applications and
Design, PWS Publishing Company, 1997
- Syllabus
Lectures
(lecture notes):
Week 1
-
Chapter 1.
Digital Systems Overview.
Positional Number Systems.
Number System Conversion. Binary Codes.
Week 2
-
Chapter 1. Arithmetic
Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10
Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18
- Chapter 2. Binary Logic Functions. Switching
Algebra.
Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10
Slide 11 Slide 12 Slide 13 Slide 14
Week 3 -
Chapter 2.
Switching Algebra. Functionally Complete Operation Sets.
Reduction of Switching Equations Using Boolean Algebra.
Realization
of Switching Functions.
Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7
- Chapter 3.
Definition of Combinational Logic. Canonical Forms.
Generation
of Switching Equations from Truth Tables.
Karnaugh
Maps.
Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 7 Slide 7
Week 4
-
Chapter 3.
Karnaugh maps. Incompletely Specified Functions.
Simplifying Maxterm Equations.
-
Quine-McClusky Minimization Technique.
Quine-McClusky using don’t care terms.
Week 5 -
Chapter 3. Map-entered variables. Mixed Logic Combinational Circuits.
Multiple
Output Functions.
Slide 1 Slide 2 Slide 3 Slide 4 Slide 5
- Midterm 1
Week 6
-
Chapter 4. Analusis and Design of Combinational Logic
Decoders. Design with Decoders.
Week 7 -
Chapter 4.
Encoders. Multiplexers. Design with Multiplexers
Week 8 -
Chapter 4. Adders. Subtractors. Comparators. ALU. Tristate Buffers
Week 9
-
Chapter 5.
Flip-Flops. Simple Counters. Registers.
Week 10
-
Chapter 5.
Flip-Flops, Simple Counters and Registers.
-
Midterm 2
Week 11
-
Chapter 6. Introduction to Sequential Circuits.
Week 12
-
Chapters 4 & 5.
Exercises related to Chapters 4 & 5.
Week 13
-
Chapter 6.
Introduction to Sequential Circuits.
Week 14
-
Chapter 7. Sequential Circuit Design. State Minimization. Equivalence Classes.
Week 15
-
Chapter 7. Map-entered variables. Mixed Logic Combinational Circuits. Multiple
Output Functions.
Exam Week
-
Final Exam: Thursday 12/21/2000 - Javits 102 Homeworks
: HW2: Page 47 Ex 32, 33, 34, 35, 36. (Due week 3)
Mealy and Moore Machines. State Machine Notation.
Design with D flip flops. Design with T flip flops.
Design with SR flip flops. Design with JK flip flops.
Up-Down Decade Counter. Sequence Detectors. Counter Design
Implication Charts. State Minimization of Incompletely Specified State Tables.
Merger Graph. Maximum Compatibility. State Assignment. Implication Graph.
HW3: Page 73 Ex 3, 4, 5, 6 Page 83 Ex 24, 27 & 29.
HW4: Page 153 Ex 11, 12, 16.
HW5: Page 154 Ex 17 Page 239 Ex 4, 5. Page 240 Ex 10.
HW6: Page 241 Ex 27 (a,b), 25 (b) Page 240 Ex 17 (e, h) Page 241 Ex 25 (b), 26 (a).
HW7: Page 242 Ex 41 & 51.
HW8:
HW9: Page 316. Ex 6. Page 317. Ex 18. Page 318. Ex 21. Page 319. Ex 33
HW10: Page 372. Exercise 11. Page 374. Exercises 13 & 15
Note:
If you want to share comments or anything else related to the class please send an
email to
adoboli@ece.sunysb.edu
Last updated November 19 2000.