ESE566

ESE 566:
Hardware/Software Co-Design
of Embedded Systems
(Graduate course)

Instructor: Alex Doboli, PhD

Credits: 3 credits

Time: Monday, Wednesday, 3:50-5:10PM, Grad Chem 128

Description:

This course will present state-of-the-art concepts and techniques for design of embedded systems consisting of hardware
and software components. Discussed topics include system modeling and specification, architectures for embedded systems, performance evaluation, and system synthesis. The course follows the top-down design paradigm based on IP cores.
Course requirements include four mini projects focused on system and IP core specification, and implementation of various
co-design tools.

This course will present state-of-the-art concepts and techniques for design of embedded systems consisting of hardware and software components. Discussed topics include system modeling and specification, architectures for embedded systems, performance evaluation, and system synthesis. The course follows the top-down design paradigm based on IP cores. Course requirements include four mini projects focused on system and IP core specification, and implementation of various co-design tools.

Goal:

Upon completion of this course, students will possess knowledge on state-of-the-art methodologies and techniques for hardware/software co-design of embedded systems. They will be able to (1) develop system-level specifications using high-level languages i.e. SystemC, (2) develop IP core models in SystemC, and (3) implement algorithms for co-design.

Upon completion of this course, students will possess knowledge on state-of-the-art methodologies and techniques for hardware/software co-design of embedded systems. They will be able to (1) develop system-level specifications using high-level languages i.e. SystemC, (2) develop IP core models in SystemC, and (3) implement algorithms for co-design.

Prerequisites:

ESE 545 (Computer Architectures), ESE 554 (Computational Models), ESE 333 (Real-Time Operating Systems) or equivalent.

Covered Topics:

Introduction to Co-Design Problem description, goals of co-design, co-design steps, existing co-design approaches, and present challenges.

System Modeling and Specification a) Models of computation (Data flow model, Task graphs, Petri nets, Finite State Machines, Extended Finite State Machines, hierarchical models).
b) System Specification Languages (SystemC). System C page
c) Project 1: IP core modeling in SystemC.

Architectures for Embedded Systems a) Single processor - coprocessor architectures, multiprocessor architectures, architectures for DSP and multimedia, reconfigurable architecures, platforms.
The Hitachi SH-DSP 7410 Hardware Manual
b) SoC: IP core based architectures, bus standards, networks on chip.
c) Sensors and sensor networks. (tentative)
d)Project 2: Modeling of an application in SystemC.

Performance Modeling a) System-level performance modeling vs. low-level performance modeling.
b) Modeling of system latency, energy consumption for hardware and software.
c) Estimation of memory requirements.
d) Stochastic modeling. (tentative)

System-Level Synthesis and Trade-off Analysis a) Hardware/software partitioning. Task binding.
b) Task scheduling (scheduling under data and control dependencies, static and dynamic scheduling, heuristic and exact scheduling algorithms).
c) IP core integration and communication synthesis: hardware and software interface synthesis, bus encoding for low power, bus architecture synthesis.
d) Project 3: Literature survey for a co-design topic.
e) Project 4: Software development of a co-design task.

Hardware IP core synthesis High-level synthesis: module set allocation, resource binding, operation scheduling, controller synthesis.

Software synthesis (tentative) Embedded software design. Software generation under memory and energy consumption constraints.


Introduction to Co-Design	Problem description, goals of co-design, co-design steps, existing co-design approaches, and present challenges.
System Modeling and Specification	a) Models of computation (Data flow model, Task graphs, Petri nets, Finite State Machines, Extended Finite State Machines, hierarchical models). b) System Specification Languages (SystemC). System C page c) Project 1: IP core modeling in SystemC.
Architectures for Embedded Systems	a) Single processor - coprocessor architectures, multiprocessor architectures, architectures for DSP and multimedia, reconfigurable architecures, platforms. The Hitachi SH-DSP 7410 Hardware Manual b) SoC: IP core based architectures, bus standards, networks on chip. c) Sensors and sensor networks. (tentative) d)Project 2: Modeling of an application in SystemC.
Performance Modeling	a) System-level performance modeling vs. low-level performance modeling. b) Modeling of system latency, energy consumption for hardware and software. c) Estimation of memory requirements. d) Stochastic modeling. (tentative)
System-Level Synthesis and Trade-off Analysis	a) Hardware/software partitioning. Task binding. b) Task scheduling (scheduling under data and control dependencies, static and dynamic scheduling, heuristic and exact scheduling algorithms). c) IP core integration and communication synthesis: hardware and software interface synthesis, bus encoding for low power, bus architecture synthesis. d) Project 3: Literature survey for a co-design topic. e) Project 4: Software development of a co-design task.
Hardware IP core synthesis	High-level synthesis: module set allocation, resource binding, operation scheduling, controller synthesis.
Software synthesis (tentative)	Embedded software design. Software generation under memory and energy consumption constraints.

Projects:

Four projects will complement the material discussed in class. First two projects are on SystemC modeling of an embedded application
and an IP core. Goals are to familiarize students with SystemC, and to teach them the IP core modeling process. The third project is on
literature survey on a co-design topic, like hardware/software partitioning, task scheduling, communication synthesis, performance
evaluation, and so on. Goal is to provide students the needed background in co-design. Fourth project will be on developing a software
implementation of the co-design task studied for Project 3. The implementation will be in C++/C. For experiments, Project 4 will use
the SystemC models built as part of Projects 1 and 2.

Project 1

Project 2

Project 3 Guidlines.

Project 4 (Due: Dec 16 12pm; Defense: Dec 17)

Course Schedule

Text Books and other Materials

1) G. De Micheli, R. Ernst, W. Wolf, "Readings in Hardware/Siftware Co-Design", Morgan Kaufman, 2002.
2) G. De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.
3) Other published papers will be provided in class.

Grading

Final grade = 0.2 * report 1 + 0.2 * report 2 + 0.2 * report 3 + 0.4 * final report